In high power linear applications that use power transistors, it is often a requirement that the current be shared among two or more parallel configured transistors to stay within the power dissipation ratings of those transistors. In such applications, the benefit achieved by parallel current sharing is reduced if one of the transistors operates in such a manner that it carries most of the current load. Difficulties have been experienced in current sharing applications due to the operating characteristics of the transistors.
In a linear mode, the operating point of a transistor typically swings from a high drain-to-source voltage (V.sub.DS) at low drain or load current (I.sub.D) to a point of low V.sub.DS at high I.sub.D. The thermal load may be substantial at even low currents, however, and to take full advantage of the field effect transistors inherent immunity to secondary breakdown there is a need to assure good current sharing from the maximum current down to a small fraction of the maximum. Thus, it is not satisfactory to only assure current sharing at high currents.
It is known that the current sharing across a wide range of currents can be difficult to achieve due to the temperature driven instability of the field effect transistor. The Motorola reference document entitled "Power MOSFET Transistor Data" (Third Edition, Second Printing, Motorola, Inc. 1988) recognizes good current sharing is difficult to achieve across a broad range of currents. The disclosure of this reference document is incorporated herein by reference. At low load currents where the gate-to-source control voltage falls below about 6 volts, an increase in the junction temperature increases the load current. This is a consequence of the decrease in the threshold voltage between the gate and source overcoming the effect of an increase in the drain-to-source DC resistance of the ON state transistor.
Inexpensive remedies to the problem of current sharing over a wide range of load currents have been difficult to achieve. In a typical application a self-biasing resistor is connected between the transistor source and ground. If a small value resistor is used for this self-biasing function, it functions well at high load currents. At low currents, however, the small value resistor becomes ineffective. If a large biasing resistor is chosen, it works well at low currents but cannot work at high currents needed in high power transistor applications.
Two prior art documents concerning the sharing of load current in parallel configured field effect transistors are a paper entitled "Techniques for Controlling Dynamic Current Balance and Parallel Power MOSFET Configurations" by Forsythe, Proceedings of Power Con 8, 1981 and U.S. Pat. No. 4,779,060 to Henden, issued Oct. 18, 1988. The '060 patent to Henden recognizes the difficulty in attempting to achieve current balance over a wide range of operating conditions. The technique disclosed in this patent for addressing this problem is to operate a parallel configured MOSFET circuit and dynamically trim gate-to-source resistances under actual load conditions to achieve current sharing amongst multiple transistors.